Homework 3
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Due Tuesday, May 19
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(Note:  Vijoy will be out of town May 16-20.)

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Use Chipmunk to design a very simple cache memory for a computer having
8-bit words and 12-bit addresses (one word per address).  The cache will
consist of 64 lines, and will be direct-mapped and use a write-through
policy.  Your cache will be able to process read hits, and write hits
and misses, but not read misses.  For the latter, you will simply
indicate a read miss on a ReadMiss line.  Also, your design will not
include the main memory, so you will not actually carry out the
write-through (the write-through comes into play here only in that
writes hits and misses are handled identically). 

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Your design must comply with the following requirements:

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<LI> 

You will use two SRAM8K chips for the cache.  The first one will contain
the Data field for the various lines, while the second will store the
Valid and Tag fields.

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<LI>

Set up three hex keypads to serve as the address input to the cache,
i.e. the CPU's MAR.  (It will be similar to the address boxes at the top
of pages 553 and 557.)

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Set up lines DataOut7, DataOut6, ..., DataOut0 to serve as the output
of the cache for read hits.  (These would lead into the CPU's MDR.)

<P>

<LI>

Set up two hex keypads to serve as inputs to the cache for writes.
If you need to avoid a clash with the DataOut lines, use tri-state
devices.

<P>

<LI>

Set up a Digital Switch to serve as the CPU's Read-Write output (1 for
read, 0 for write), which is input to the cache, telling the cache
whether it must perform a read or a write.

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<LI>

As indicated above, you will also have as output from the cache a
ReadMiss line, which is 1 for a read miss, 0 otherwise.  (This would
normally feed in to mechanisms to process the read miss from main
memory, but this is too complex for us at this point, so we will
not do this.)

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