Homework II/III

Due Tuesday, October 21; counts as TWO assignments

Problem I.

Implement the two- and three-bus versions (for Extra Credit, also do the one-bus version) of the bus-based circuit on p.16 of our PLN unit on digital design, as follows:

• Each register is 8 bits wide (instead of 1 as in the PLN). Use Chipmunk hex keypads (in the case of R0 and R1) to enter values into registers. Use hex displays to check what is in registers R0 and R1.

  Note that registers R0 and R1 not only accept input from a bus, but also for test purposes accept input from hex keypads. So, you will need to use tri-state devices to connect/disconnect the keypads and their registers.

• The ALU is capable of doing addition, subtraction, logical AND and logical OR, with op codes 0, 1, 2 and 3, respectively. Each instruction includes two 1-bit operands, src and dst, indicating the source and destination registers.

  By definition, dst is the register which changes value as a result of the operation. The subtraction operation computes dst-src. Note that dst and src can only be R0 or R1, not the private registers (make sure you understand why). The case dst = src is definitely allowed.

  Storage is assumed to be in 2s complement form. The output of the ALU is truncated to the lower 8 bits. The ALU must be implemented as a Chipmunk module.

• The op code is input to the ALU from the lower two bits of a hex keypad. Use the upper two bits to specify the source and destination registers. For example, suppose you wish to do the operation

  R1 <- R1 OR R0
  

  Then you would put 0111 in the hex keypad: 0 to indicate src = R0, 1 to indicate dst = R1, and 11 to indicate op = OR.

• In the three-bus system, you have no private registers. In the two-bus system, you have just R2. If you do the Extra Credit one-bus system, you have private registers R2 and R3.

• Implement the clock as a Chipmunk digital pulse-generative switch. It will feed into a counter which keeps track of how many clock cycles have been completed so far in the current operation (add, subtract, AND, OR). (If you are not doing the Extra Credit, you can make your counter a single flip-flop, say a J-K flip-flop used in toggle mode.)

  Note carefully that you will use this counter to determine which registers to connect to the bus at any given time. Since the AS and AD lines control the tri-state devices at the registers, then the circuitry near the counter should place the proper register numbers on the AS and AD lines at the proper times. If in a given clock cycle R1 is to be copied to R3 via a certain bus, the counter circuitry here should place 01 onto the AS lines and 11 onto the AD lines.

  You will probably also need to use the counter to connect/disconnect the ALU from a bus if there are fewer than three buses.

  Actually, since neither R2 nor R3 will ever be copied to a bus, you could have just a single AS line per bus. If you wish, you can take this idea a step further, and not connect R2 or R3 to buses at all. Then you would have direct transfer from one of R0 and R1 to R2 or R3, and you would hae just a single AD line per bus as well.

• A typical test of your circuit will consist of your loading a value into the hex keypad, and then pulsing the digital pulse-generative switch one to three times, depending on the number of buses.

Some advice:

• Note that in this problem you are building (close to) a full CPU, similar to what is shown on p.22 of our PLN unit on digital design. The main difference is that you are inputting the instructions "by hand," via a hex keypad, so you will have no IR, MUX, etc.
• "Start small," by first implementing the simpler register/bus system on p.15, making sure to add the necessary testing machinery.
• The three-bus system is the easiest, since there is no clock cycle counting, so start with it.

Note that things like resetting the clock counter must be automatic. Suppose for instance that you will do two consecutive add operations, with no input "by hand" to the second one (i.e. the second one just uses the output of the first). For a two-bus system, those two operations should take four clock cycles, i.e. four consecutive clock pulses; you may not do an extra cycle by hand to reset the clock.

Problem II:

Part A:

The 7400 chip available in Chipmunk is apparently not like the real one. It implements just one NAND gate, not a quad set as on p.50 of Dandamudi. Create a Chipmunk module which does implement a quad set of NANDs. Set up the same pin arrangement as in the 7400 (minus power and ground). Name your module MYNAND4. Test your module.

Part B:

Create a 4-to-1 MUX by using only MYNAND4s. (Make an attempt to use as few as possible, but you need not be sure it's minimal.) Make a Chipmunk module out of this, naming it MYMUX4. Test your module.

Problem III:

Consider the 4-variable boolean function

F = ABC'D' + AB'C'D + A'B'CD + A'BC'D + AB'CD' + A'BCD' +
ABCD' + ABC'D + AB'CD + A'BCD 

where the ' symbol here means NOT. In words, F expresses the condition that exactly two or three of the four inputs are equal to 1.

Using a Karnaugh map, simplify the above expression for F.

Write up your solution as a plain ASCII text file. Use lower-case letters next to 1s to indicate groupings. For example, Fig. 2.16(a) in Dandamudi could be drawn as

  BC   00   01   11   10
 A                   
 0     0    0    1v   0   
 1     0    1u   1uvw 1w  

Here I have set up groups named u, v and w. The entry 1uvw indicates that that cell belongs to all three groups.

Be complete in your writeup. For instance, in the example above you would write something like, "The cells in group v all have the property that B = 1 and C = 1, so this group represents BC."