Cyclic Redundancy Checking

Norman Matloff
Dept. of Computer Science
University of California at Davis
©2001, N. Matloff

May 5, 2001

1  The Importance of Error Detection

A transmitted bit can be received in error, due to ``noise'' on the transmission channel. If we are dealing with voice or video data, the occurrence of errors in a small percentage of bits is quite tolerable, but in many other cases it is crucial that all bits be received intact. If for example we are downloading a binary program file, the program may be unexecutable if even one bit is incorrect. If the destination or source address of a packet has one bit wrong, communication is impossible.

There are many methods which have been developed to detect errors, applied at different levels of the seven-layer model. Of course, no method can detect all errors, but a number of methods in use today are amazingly effective. The one we will discuss here is the famous CRC coding form.

2  The CRC Error-Detection Method

One powerful error-detection method is Cyclic Redundancy Checking (CRC), a generalization of parity checking. One appends a few (typically 16 or 32) bits to the end of the bit string for a message and sends out the extended string. The receiver then performs a computation which would yield 0 if no bits of the message had been in error; if the result is not 0, then the receiver knows that there has been an error in one or more bits.

CRC cannot detect all possible errors, but the range of errors which it can detect is impressively broad. As networks textbook authors Larry Peterson and Bruce Davie have pointed out, it is quite remarkable, for instance, that a mere 32 bits of CRC are sufficient to provide adequate protection against errors in the 12,000-bit messages which Ethernet can send.

3  How CRC Works

Let M be the message we wish to send, m bits long. Let C be a divisor string, c bits long. C will be fixed (say hardwired into a serial I/O chip), while M (and m) will vary. We must have m > c-1. It is always assumed that c > 1 and that the first and last bits of C are 1s.

Our CRC field will consist of a string R, c-1 bits long. Here is how to generate R, and send the message:

For example, say C = 1011 and M = 1001101. Then we divide as follows:

1011 
1010011
)
1001101000
1011
0

  1010
  1011
2

     1100
     1011
4

      1110
      1011
6

       101

We first divide 1011 into 1001 (see above), with a quotient of 1. Yes, that's right! As long as the dividend has at least as many digits as the divisor-both have 4 digits here-then the divisor does indeed ``go into'' the dividend with a quotient of at least 1. If they have the same number of digits,1 the quotient is 1, which is placed as the first digit in the overall quotient above the division sign. Our remainder is 0010 (remember, our arithmetic here is mod 2, bitwise), which we write as 10.

Next we extend that 10 by bringing down the next digit in the dividend, a 1, forming 101, that is 0101. 1011 goes into 0101 0 times, so we place this 0 as the next digit in the overall quotient above, and bring down the next digit of the dividend, a 0, making 1010. Now 1011 goes into 1010 1 time, and so on.

The final remainder is 101, so the transmitter now sends the string 1001101101.

(You should check that one can ``multiply'' back to get the original result, i.e. 1011*1010011 + 101 = 1001101000. Remember, though, that the multiplication and addition are done on a mod-2 basis, i.e. XOR with no carries.)

The receiver then receives a string Y, which is hopefully the same as W but might not be, due to line noise. The receiver divides Y by C; if the remainder is nonzero, the receiver decides Y had one or more bits in error, while if the remainder is zero, the receiver accepts Y as correct (though it still might not be).

4  Why It Works

Note that the replace operation in step 3 above is equivalent to performing


W M+R
(1)

Moreover, because we are using mod 2 arithmetic, that operation is also equivalent to


W M-R
(2)

If one divides, say, 63 by 5, then one gets a remainder of 3. That means that if we subtract that remainder of 3 from the dividend 63, the result 60 will be evenly divisible by 5.

Similarly, since R was our remainder from M'/C, we see from the last equation that M'-R is exactly divisible by C. So, W is divisible by C.

Let E denote the error vector, a symbolic way to describe which bits in W get corrupted on their way to the receiver. If for instance the i-th bit of E is a 1, this means that there was an error in the i-th bit of W. Then the receiver will receive Y = W + E, again keeping in mind that this is mod-2, bitwise addition.

We hope E consists of all 0s, of course, but it might not. The receiver will divide Y by C; since W is evenly divisible by C, then Y will be too if E = 0. So, if the receiver finds that Y/C has a nonzero remainder, the receiver can be sure that there was an error.

In other words, the CRC will detect all error patterns except those for which E is evenly divisible by C. Clever people have found good strings C for which a remarkably small proportion of Es are evenly divisible by C. These Cs have been publicized and are in common use.

Note that E is an m+(c-1) bit quantity, so it includes the bits corresponding to the R portion of W. So, the system here is even capable of detecting some errors in the CRC field itself!

By the way, when we divide M' by C, getting a quotient Q and a remainder R, Q will be m bits long. To see this, draw a ``long division'' diagram as above, and note that the first and last bits of Q will be above the c-th and (m+c-1)-st bits of M', so that Q consists of (m+c-1) - c + 1 = m bits.

5  What Kinds of Errors Will CRC Detect?

In CRC analysis, it helps to represent bit strings as polynomials. For instance, our C above, 1011, would be denoted by


x3+x+1
(3)

The word ``denoted'' here is key; the polynomial is just notation, and there is no physical variable x. But this notation turns out to be an extremely powerful tool for analyzing CRC. We will use C(x), E(x) and so on to refer to the polynomial versions of the bit strings C, E etc.

The question at hand is which types of E strings are detectable by which C strings. Remember, we decide what string to use for C, say when we design a serial I/O chip or Ethernet interface card. So, we want to choose C in such a way that many classes of E strings are detectable. Recall that an E string will be detected as long as C does not evenly divide it, and our analysis will stem from this consideration.

Following are two examples of the many properties CRC theorists have proven.

6  Digital Implementation

As you can see, the CRC algorithms could easily be encoded in software, but that may be too slow. It would be much faster if implemented in digital logic hardware, and it turns out that this can be done quite simply.

As before, let c denote the number of bits in the divisor polynomial C(x), so that the degree of the polynomial is c-1. Then we set up a left-to-right shift register with c-1 bits, which we will denote, from left to right, S0,S1,...,Sc-2. . As with any shift register, at each clock impulse Si is replaced by the value which had been in Si-1 , where we are calling the left input `` S-1 .''

However, our shift register will differ from an ordinary one in that at each clock pulse the value which had been in Sc-1 will be recycled and XOR-ed with some of the other Si . Specifically, if there is a term xj in the divisor polynomia C(x), then there is an XOR just to the left of Si (except for i = c-1).

The message M, with c-1 0s appended as before, is fed into the input to the shift register, one bit per clock cycle, starting with M's most significant (i.e. leftmost) bit. After m+c clock cycles, the shift register contains the remainder (i.e. the CRC field), in reverse order.

Our figure here shows the setup for the case C(x)=x3+x+1 , i.e. C = 1011, from our example above.

Figure

The table here shows a pulse-by-pulse account of what will occur with the input M = 1001101 (with three 0s appended):

clkinputS0S1S2
01000
10100
20010
31001
41010
50101
61100
70110
80011
90110
end101

For example, at the end of clock period 3, the register contains (0,0,1), with an input of 1 coming in, say, near the end of the clock period, taking effect in the next period. Then the clock pulse starting period 4 comes. What happens?

So, the new register state will be (0,1,0), seen in row 4.

This would occur at the transmitter end, and a similar setup for the CRC check will be at the receiver end.


Footnotes:

1The number of digits is counted beginning with the first 1 digit, so for example 0011 is considered only a 2-digit quantity, not a 4-digit one.


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On 8 May 2001, 16:33.