Homework 3

Due Monday, February 22

In both problems here, you will use Chipmunk/diglog to build pipelines. Be sure to follow all the specified modularization; this is REQUIRED. Make sure to work on Problem I first, before even thinking about Problem II; pipelining has subtle difficulties, so it is crucial that you do an "easy" (or easier) one first.

Also, remember that we are using the new homework turn-in policy for the rest of the quarter, involving the cheksum.

Problem I:

Build the polynomial pipeline as described in our handout on pipelines. The values of x, a, b, c and d are 4-bit unsigned integers. Do not worry about overflow (i.e. ignore it).

You are required to have the following modules:

• Multiplier:

  Inputs consist of the 4-bit multiplicand and 4-bit multiplier, and output consists of the product, truncated to the lower 4 bits.

  Use the straightforward "pencil-and-paper" approach: You will sum together four 8-bit numbers, each one of which is either a shifted version of the multiplicand (in the case in which the corresponding bit in the multiplier is a 1) or a string of 0s (in the case in which the corresponding bit in the multiplier is a 0).

  Note carefully: Do NOT use a shift register to get the shifted bit strings. Instead, simply "offset" the wires. For example, let our 4-bit multiplicand be rstu, and call the shifted version vwxyz. Simply route wires from r to v, from s to w, from t to x, and from u to y, and attach z to 0.

• Pipe Stage:

  Inputs consist of: x; the result of the previous stage (or a, for the first stage); and the constant b, c or d. Outputs consist of the a 4-bit arithmetic result, again truncated, plus the 4-bit value of x.

  This module will consist of a Multiplier, an Adder (just use one from the Chipmunk catalog), and registers to latch x and the output of the previous stage.

Of course, use a Digital Pulse Generative Switch as your clock.

Problem II:

Implement a pipelined floating-point addition unit, according to the following specifications.

The numbers will be 6 bits long, with the leftmost (i.e. most significant) 4 bits forming the mantissa m and the last 2 bits comprising the exponent e (which is for a power of 2). The m field is to be considered to be an unsigned integer, while e is a 2s-complement signed integer. (Thus negative floating-point numbers cannot be stored.)

Make sure to verify for yourself that

 
010111 + 001110 = 110110

So, if 010111 and 001110 are input to the first stage of the pipe, the output from the last stage will later be 110110.

If you need review on floating-point numbers, please click here. As always, feel free to ask the TA and/or me any questions on this.

The pipe will consist of 4 stages:

• S1:

  Compare exponents of the addends.

• S2:

  If one exponent is (algebraicly) larger, change it to match the smaller one, and shift left its mantissa to compensate. In order to simplify matters, assume that (a) overflow due to the mantissa shift will not occur, and (b) the exponent of the second addend will always be algebraicly less than or equal to that of the first.

• S3:

  Add mantissas, forming a 5-bit sum.

• S4:

  If the most significant bit in the result of S4 is a 1, shift the mantissa right one bit, and adjust the exponent accordingly. (Ignore any overflow in the exponent.)

You are required to have one module for each stage above.

Again, your design must be PIPELINED. Assuming new inputs are constantly fed into the pipe, there will be floating-point additions for 3 separate pairs of numbers in progess simultaneously.

Again, do NOT use shifter components. Instead, just route wires "diagonally" as in Problem I.