Problem I:

Use diglog to implement an 8-bit multiplier using the scheme in Fig. 4.26. It is required that you build and use the following modules (see the mini-manual for instructions on how to build and use modules):

• An 8-bit shift register, using two SHIFT components.

• A 16-bit shift register, using four SHIFT components.

• A 16-bit adder, using four 7483 components.

Since the largest module "instance gate" allows only 42 pins, we cannot implement the 16-bit adder in one module. Instead, make a module for an 8-bit adder and use two such modules in your overall circuit.

Make sure you test these modules thoroughly before building the circuit as a whole.

Problem II:

In this problem, you will explore the effects of block/line size on the cache performance. You will take a C program, Sort.c, and run it through a simulator of the DLX processor to get a record of memory references, and then run the latter through a cache simulator which will count cache misses and related statistics. Sort.c is available in my home directory on the CSIF machines.

Assume a unified cache with size of 8K and a write-back policy.

Write up your solutions to the problems below in a plain ASCII text file, which will be read by the Reader.

(a)

Tabulate the number of misses versus the block/line size, with values of the latter being (in bytes) 4, 8, 16, 32, 64, 128, 256, 512 and 1024. You should observe a "U shape" as in Fig.7.12, p.559. (But just tabulate, not graph, the data.)

(b)

Now assume the machine has a block/line size of 4 words, i.e. 16 bytes. In this problem, you will modify the program to get a lower miss rate.

You are allowed to make any modifications to the declarations in the program, both global and local, but you are not allowed to change the code in any manner. Changes to the declarations can be of the following types:

• Changing the order of the variables.

• Changing to the C language's "register" type.

• Adding fake variables to create "filler" space.

Your goal is to reduce the number of cache misses.

To receive full credit for this problem, you need only make enough changes to produce some reduction in misses. But I am also making Extra Credit available; the six homework groups having the least numbers of cache misses will have their Exam II letter grades raised two notches as with the Extra Credit in the previous homework.