Note: Problem I is required. Problem II is for Extra Credit; you will have your midterm grade raised if you complete it correctly (details given below).

In both problems here you will use use Chipmunk to design a very simple cache memory for a computer having 2-bit words and 7-bit addresses. The cache will consist of 16 lines, one word per line. For simplicity, we will assume that the memory system is read-only, i.e. the CPU will only generate reads, not writes. (Think of the main memory as consisting of ROM, so data are already there.)

It is required that your design be implemented as follows:

• Use SRAM8K chips for both your cache and your main memory, (pretending that the cache one is faster). Use one SRAM8K chip for your main memory, and use one (for Problem I) or two (Problem II) for your cache.

• Use a 16COUNT component (or a TNEG flip-flop if your design needs only two clock cycles) to count clock cycles. As usual, do not put a "real" clock in your circuit, but rather a Digital Pulse-Generative Switch; pulse it manually either once, twice or thrice, as needed.

• The "output" of the cache access will consist of two wires which contain the requested memory word, and a Read Completed bit wire; the latter will be equal to 1 after one cycle in the case of a hit, three cycles in the case of a miss.

• Set up two hex keypads to serve as the address input to the cache, i.e. the CPU's MAR (similar to the address boxes at the top of pages 553 and 557), a hex display and LED for the output.

Problem I:

Implement the cache as direct-mapped. Use one SRAM8K for your cache. Each word in your cache SRAM8K will store one complete line of the cache---Valid bit, Tag and Data.

Problem II:

Implement the cache as 2-way set-associative, using the LRU scheme given in the textbook. Use two SRAM8Ks for your cache. Each set in your cache will be implemented in corresponding words within the two SRAM8Ks which comprise your cache. For instance, set 3 of your cache will be in words 3 of the two SRAM8Ks. Each of these corresponding words will contain a Reference bit, a Data field, a Valid bit and Tag bits for the given line.

Hints for both problems:

Always start simply. In both problems, don't implement the mechanisms for misses at first; simply design your circuit as if all accesses will be hits. Once you have that working, add the circuity to handle misses.

In the miss part of Problem I, and even in the hit part of Problem II, you need to count clock cycles, with the circuitry doing different things on different clock cycles. This is because you can't read and write an SRAM8K during the same cycle. Before attempting those parts of the problems, look at the "fetch-and-add" example in my diglog mini-manual. Make sure you understand the use of TNEG and the tri-state buffers.

In Problem I, during the first clock cycle you will check for a hit, and if there is a hit, produce the required output. In the case of a miss, the requested word is brought in to the cache (and to the cache output) from memory during the second clock cycle.

In Problem II, note that the Reference bit must be updated even in the case of a hit. Thus, you read the cache in the first cycle and then even if there is a hit you write to the cache during the second cycle. Again, I strongly recommend that you implement this before attempting to implement miss-handling.

If you wish, you can also fetch from memory during the second cycle in the case of a miss. The advantage of this is that you would only need two clock cycles to do the entire operation (and thus you could use TNEG for your cycle counter, instead of 16COUNT). On the other hand, you may feel it is easier to do a miss-replace in a separate cycle, thus taking three cycles in all in the case of a miss; it is up to you which approach you take.

Rules for extra credit in Problem II: If you complete Problem II correctly, your grade on Exam I will be raised by two "+- notches." For example, a C- would become a C+, a B would become an A- and so on.