Homework 4
<BR>
Due Wednesday, June 3

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Problem I:

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In this problem you will use Chipmunk to implement age registers for LRU
checking in a cache.

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Set up four 4-bit counters, corresponding to age registers for a set of
four lines.  Inputs will be:

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<UL>

<LI>

A clock line.

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<LI>

A hit/miss line.

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<LI>

A 2-bit quantity which indicates which line is accessed, in the case of
a hit.

</UL>

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On each clock cycle (which we assume has already been AND-ed with a
line choosing this set), every counter is incremented except for one
which is reset to 0.  The exceptional line is the one accessed in the
case of a hit, and the one replaced in the case of a miss.  Also, if
upon incrementing, one of the registers wraps around to 0, all the
registers are reset to 0.

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As usual, remember that we are just implementing part of a system.
The inputs here would be outputs from other parts of the system.

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Problem II:

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In this problem you will get a chance to explore how block size and
other cache hardware parameters, and even the way we write our code will
affect the speed of a program.  You will use the <A
HREF="http://heather.cs.ucdavis.edu/~matloff/dlx.html">DLX architecture
simulator</A> and the <A
HREF="http://heather.cs.ucdavis.edu/~matloff/dinero.html">dinero cache
simulator. </A>

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(Note:  Parts of this problem require you to report some numbers and 
give explanations.  Write these up in an ASCII text file.) 

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Part A:

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Consider the program

<PRE>

int Z[1000];

main()

{  int I;

   for (I = 0; I < 1000; I += 4) Z[I] = I;
}

</PRE>

Compile and run the program, and then run dinero with a 16-byte block
size, a 16K unified cache, and set-associativity of degree 4.  Do two
runs, one with write-through and the other with write-back policy, and
compare the two amounts of memory traffic generate.  

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Explain why one worked better than the other on this particular program.

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Part B:

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Here you will be using the program Prime.c in the directory

<PRE>
~matloff/Pub/DLX
</PRE>

on the ACS machines.  (Note that this program differs slightly from
the program of the same name on my DLX Web page.)

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Compile and run the program, and then do several runs of dinero, noting
the instruction and data cache miss rates and amount of memory traffic
in each case:

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<DL>

<DT> (i)

<DD>

block size 64, unified cache size 1K, set-associativity 1,
write-back policy

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<DT> (ii)

<DD>

block size 64, instruction cache size 512, data cache size 512,
set-associativity 1, write-back policy

<DD>

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<DT> (iii)

<DD>

block size 64, unified cache size 1K, set-associativity 4,
write-back policy

</DL>

Explain the reasons for the difference between the results of (i) and
(ii), and between (i) and (iii).

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Part C:

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Again use the program Prime.c.  Assume that it takes 15 cycles for each
word read/written from/to memory, on top of the number of cycles
reported by dlxsim for executing the program.  Assume the cache
parameters in B(i) above.  Modify Prime.c so as to reduce its
overall run time (measured in total number of cycles, i.e. the sum
of the basic cycles reported by dlxsim and 15 times the number of
memory words accessed as reported by dinero).  

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The six homework groups having the six fastest programs will get
Extra Credit.  (The Reader will record this and give me the results.)