Due in stages
Problem 1, due Thursday, November 6:
Here you will implement a memory system with the following specs:
- The size of the system is 32Kx4.
- Use low-order interleaving.
- Use four of Chipmunk's SRAM8Ks for the memory modules. (The word
module here is used in the sense of a physical portion of memory,
rather than in the Chipmunk modular design sense.) In your Chipmunk
circuit, label them M0, M1, M2 and M3, where Mi contains all system
memory addresses which are equal to i, mod 4.
- Store each 4-bit system word in the lower four bits of an SRAM8K
word, leaving the upper four bits unused.
- You will have bus lines A0, A1, ..., A14, data lines D0, D1,
D2, D3, and an R line (high for read, low for write).
- Simulate the CPU by connecting a hex display to the Di to show the
value read, a hex keypad connected to the Di to contain data to be
written, and four hex keypads for the address and R (all but one bit of
the 16 from these last four keypads are connected to the address lines,
and the R bit is connected to the R line).
- Remember, the purpose of a bus is to enable communication between
various devices, in this case between the CPU and memory. Make sure you
stick to this, i.e. you have the CPU communicate with memory only via
the bus and not directly.
Be extra careful in testing, as some errors might be masked if
you do not test carefully.
- Use the CNFG mode on the four SRAM8Ks to see that the correct
values have been stored in the correct SRAM8Ks. For example, say you
wanted to put 12 into address 15 of the computer's address overall
memory space, which should be in address 0000000000011 of M3. So, check to
see that that address in M3 really does contain 12. (Note: The TA will
be checking in this manner during the grading process.) Make sure you
check all modules.
- Make sure you check both reads and writes.
Problem 2, due Friday, November 14:
Here you will develop a 16Kx4 memory, using a single SRAM8K chip.
Addresses 2k and 2k+1 of the system memory will be stored in the lower
and upper four bits of address k of the SRAM8K chip, k = 0, 1, ...,
8K-1; note that system addresses are 14 bits wide, whereas SRAM8K
addresses consist of only 13 bits. The memory will be read-only (which
simply means that you don't have to worry about writes; no special
circuitry is needed).
Your bus will consist of lines A0-A12 (not A0-A13) and D0-D7. Note
that the latter means that you fetch two system words, not one, with
each memory access, a scheme intended to improve overall speed. We will
use the terms requested word and co-word, respectively, to
refer to the system word the CPU currently wants to fetch and use, and
the other system word stored in the same SRAM8K word.
Your simulated CPU will be a bit complex, consisting of the following:
- a 14-bit (not 13-bit) address register, for the address of the
- a 4-bit data register, for the requested word
- a 36-bit cache, consisting of two 18-bit cells; each cell contains a
14-bit address and a 4-bit data item (note that the term cache
here is only meant to convey the spirit of its functionality, rather
than implying the exact form of the caches we are studying in class)
- "glue," i.e. miscellaneous circuitry in the CPU to make the data
register and cache work properly
Here is what these various components do:
- The glue will first check to see whether the requested item is in
the cache, by comparing the value in the address register to the two
addresses in the cache. If the item is in the cache, the glue will copy
the item from the cache to the data register.
- If the item is not in the cache, the glue will place the proper
13-bit address onto the bus, in order to fetch the requested word and
its co-word. The glue will copy the requested word to the data
register, and will copy to the cache both the requested word and its
co-word, along with their addresses.
You will need at least one clock pulse, in order to load the data
register, and if appropriate, the cache. Feel free to use more than one
clock cycle if you need it. Similarly, feel free to have a counter for
clock pulses, to serve as a state indicator. Of course, you will have
various hex keypads and displays, e.g. a keypad in order to load the
address register with a test address.
As you know, Chipmunk does not have any refined notion of timing. Thus,
short of putting in artificial delays, we cannot model the fact that
cache access is faster than memory access. Nevertheless, to make things
realistic, make SURE that the CPU does not put an address on the bus
until after it has found that the requested word is not available in the
Load your test data into the SRAM8K either by loading from a disk file
or by using CNFG mode.
The nominal due date for this problem is Wednesday, November 12. This
means that I will be open to extending the due date if, as November 12
approaches, I find that most students have made considerable progress on
this problem but could use some extra time.